Given how SRAM-intensive modern designs are, SRAM cell size and density are major characteristics of new fabrication technologies. Apparently, the SRAM density of Intel's 18A manufacturing process ...

TSMC is on track to start high-volume production of chips on N2 (2nm-class), its first production technology that relies on gate-all-around (GAA) nanosheet transistors, in the second half of this year ...

TSMC's next-generation N2 process has officially booked its first customers: Apple, MediaTek, and AMD, with NVIDIA reportedly paying a hefty premium to get pole position for A14. Notably absent from ...

TL;DR: TSMC's 2nm (N2) process, featuring advanced Gate-All-Around transistors (GAAFET), promises significant efficiency and performance gains over 3nm. Major tech companies like AMD and Intel are ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows have been certified to support TSMC’s new Design Rule Manual (DRM) ...

SANTA CLARA, Calif.--(BUSINESS WIRE)-- TSMC (TWSE: 2330, NYSE: TSM) today showcased the newest innovations in its advanced logic, specialty, and 3D IC technologies at the Company’s 2022 North America ...

Bottom line: Intel and TSMC are both gearing up to launch their respective 18A and N2 process nodes, each offering significant advancements. On one side, Intel claims 18A will deliver much higher ...

TSMC revealed its plans for its N2 2nm silicon production earlier this month, and has now revealed more details about it. In addition to switching from FinFET to a gate-all-around (GAA) design using ...

SANTA CLARA, CA, Jun. 16, 2022 – TSMC today showcased its advanced logic, specialty and 3D IC technologies at the company’s 2022 North America Technology Symposium, with the next-generation N2 process ...

Companies accelerate AI, hyperscale and mobile IC development on N3E and N2 nodes Mutual customers actively designing with N3E and N2 PDKs Cadence flows supporting TSMC’s latest nodes provide optimal ...