EDN

SystemVerilog assertions unify design and verification

The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language in a consistent way to include enhanced modeling and verification features. By adding verification ...
EDN

One Verilog or two? Language rift looms

Santa Cruz, Calif. – With the failure of the Accellera standards organization to meet an August deadline for technology submissions to the IEEE committee working on Verilog 2005, the risk of two ...
Business Wire

Verific Ships First Commercially Available SystemVerilog Parser

Verific Design Automation, the leading provider of Verilog and VHDL front ends for electronic design automation (EDA) applications, today announced that it is shipping the first commercially available ...
Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

"VeriEZ is strongly committed to supporting technologies that enable wide-spread adoption of the SystemVerilog language. The Advanced Verification Methodology (AVM) is sure to add tremendous value to ...
Electronic Design

Getting To A Higher Level

SystemVerilog, itself in the midst of the IEEE standardization process, is the subject of the IEEE's P1800 working group. By the time this article is published, that working group should have ...
Electronic Design

Writing Testbenches Using SystemVerilog

Survey hardware design teams and you’ll find that the old saw is true: anywhere from 60% to 80% of the overall design cycle is consumed not with design itself, but rather with the nerve-wracking ...
Design-Reuse

DVCon speaker compares assertion languages

SAN JOSE, Calif. — Why are there two standard assertion languages — Property Specification Language (PSL) and SystemVerilog Assertions (SVA) — and how do they compare? John Havlicek, principal staff ...
Design-Reuse

Novas Extends Industry-Standard Debug Platform with Faster Performance and Advanced SystemVerilog Capabilities

Verdi Debug System Takes on Bigger, More Complex Chip Designs, Enables Further Automation of SystemVerilog Assertion and Testbench Debug SAN JOSE, Calif. -- July 9, 2007-- Novas Software, Inc., the ...
Semiconductor Engineering

Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...
Semiconductor Engineering

Co-Design Automation, Inc.

Knowledge Center Entities Co-Design Automation, Inc. Created Superlog, a foundation language for SystemVerilog LAST UPDATED ON May 26th, 2014 Description Co-Design created the Superlog language, based ...