EDN

Statistical Static Timing Analysis – A Better Alternative

Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or ...
Semiconductor Engineering

Static Timing Analysis: Cell Delay Vs. Cell Drive Strength

Have you ever wondered how a predator succeeds or its prey escapes in the jungle? It’s the breathtaking speed and agility of the predator (say, a leopard) as it chases prey (say, a deer). The VLSI ...
Embedded

Static timing analysis: bridging the gap between simulation and silicon

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...
EDN

Researchers call for fundamental shift in timing analysis

MONTEREY, Calif. — Calling for a new approach to the design of digital circuits, researchers at the ACM/IEEE Tau workshop here this week (Dec. 2-3) presented strong arguments for a move to statistical ...
Electronic Design

Timing Checks Go Full Chip

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...
Semiconductor Engineering

Closing The Post-Silicon Timing Analysis Gap

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...
Electronic Design

Interview: Cadence's Anirudh Devgan Talks About Parallel Timing Closure Signoff

System-on-Chip (SoC) developers are creating larger and more complex solutions. Static timing analysis and closure is key to successful solution so timing sign off tools can have a significant impact ...